In the newsgroup sci.electronics.design, a fellow pointed me to this old PE construction article. What was interesting about it was that they used a transistor based phase shift oscillator in it. The articles are found here:
http://www.swtpc.com/mholley/PopularElectronics/Apr1968/PE_Apr1968.htmhttp://www.swtpc.com/mholley/PopularElectronics/May1968/PE_May1968.htmThe Fig 5 circuit is directly here:
http://www.swtpc.com/mholley/PopularElectronics/Apr1968/PE_Apr_1968_pg46.jpgThe first thing to grab me was the small caps used and how tube-like the values seemed (in range). See C19, C20 and C21. However, I suspected that this may be running from a fairly high voltage. It turns out from looking at the May Part 2 article, that it is indeed running from nearly 60 volts, like the power stage does.
So this caused me to go back and take a new look at using a transistor only circuit. There is nothing wrong with using opamps but part of the purpose of this project is to learn how to engineer discrete designs.
Since I had a split supply for the TL072 opamp at +/-12 volts, I went back and designed for a 24 volt total supply. This extra voltage gives the stage more power to work with. This helped a lot but was not quite there yet. It worked well, but still lacked the range of adjustment I wanted. I had to have a minimum of 2Hz to 10Hz.
At that time I had C4=100uF as a bypass capacitor. But doing the math, I soon realized that even at 10Hz, the reactance was 159 ohms! To get higher gain I needed to reduce that. Notice in the magazine article how they used C18=200uF. 200uF reduces the 10Hz reactance down to 79 ohms! That bypass difference bosted gain enough to almost be good enough.
Then I studied the bias arrangement used throughout the project. Look at Q3 & Q4. This arrangement is used for all of the small signal circuits. I would have used a normal voltage divider on the base of Q3, but this circuit gets its bias from R22, R15 and R14. So this got me to thinking, why do it this way? This requires extra parts and an additional bypass cap C12.
So how does that work? Maybe that will answer the "why".
The Q3 collector is direct coupled to Q4, so this means that the Q4 emitter will be about 0.6V less than its base, and hence the collector of Q3. Q4 is an emitter follower (buffer) so all of the current is shared between Q4 and emitter resistor R19. For best swing, the voltage across at the emitter of Q4 would be about half of +60 volts, so assume about 30. This voltage is then divided between R16 and R15. So the bias voltage is developed across R15. Note that C12 bypasses R15, making that point appear as a
signal ground.
Once you realize that the top of R15 is signal ground, then you realize that R14 establishes the input impedance. Bingo! There is very little current flowing into the base of Q3, hence the voltage across R15 appears also at the base of Q3 (it takes current in R14 to establish a voltage across it, but there is virtually none).
The most important design aspect of this bias configuration is that this gives you full control over the input impedance of that stage.
That was my big breakthrough. With the traditional voltage divider approach, it was difficult or unsafe to establish an input impedance of 100k that I was looking for. To get a long RC time constant, you either need to increase R or C or both. I wanted to keep C size down to avoid big leaky caps. I also need non-polarized caps, so I need to see what range of values I can buy those in. They tend to be small caps.
In the phase shift part, I am still using C=4.7uF, which is still larger than I wanted. This requires R=100k to get it to work at 2Hz minimum. R3 and R4 are the ganged 100k pots. The magazine project managed it with one pot, but they are also operating at near 60 volts. I want to stay within the opamp rails for the non-power stages. I may someday try an all discrete design at 60 volts but not right now.
It is worth mentioning that the C7 (in my circuit) does not need to be as large as the emitter bypass. I am using 20uF there. This causes some negative feedback at the lower frequencies, which seemed to help the sine wave slightly. The higher freqs seem to clean up automatically because they need more gain, which is fixed.
Like the earlier posted opamp version of the osc, I am using two LP filters on the output. This helps the 2Hz signal shape a lot. Note also that this oscillator uses the buffer output in the phase shift feedback circuit. In the LTspice simulations, this definitely helped the sine purity since there was never any lack of drive from the buffer Q2. Q1 is operating with low collector current and is the weaker member.
The only thing I might do next is to try to see if I can operate with higher R in the RC component, and use smaller C. I plan to replace my opamp circuit that I currently have soldered in place. There is something wrong with my ganged pot (it clicks) among the other problems previously mentioned.
But dead bug style makes it easy to undo and redo. This is perfect for experimentation. Hope you enjoyed reading this design discussion as much as I have had learning about it.
Attachments:
There is an output waveform for 2Hz shown. The 2nd is a FFT chart showing the low range center frequency is about 2Hz. The third is obviously the schematic.
